Application Optimization with Compilers for LOP

An anonymous reader writes "Interested in tuning your C/C++ applications for Linux on POWER? This article compares the optimization options for both Linux on POWER C/C++ compilers: GCC and IBM XL C/C++. This paper also reviews tactics, such as Interprocedural Analysis, Profile Directed Feedback, and High Order Transformations, which are used by one or both of the compilers to extract higher performance from the Power architecture."

Re:What?

[bhima]

POWER is IBM's CPU archtecture. Hope that helps

what the hell

[giel]

I cannot be the only one reading this thinking "What the hell is Linux on POWER?"

For sure you're not the only one. Almost everybody nowadays starts posting before even reading an article and or related links. Very 'Insightful'.

Re:what the hell

[Sparr0]

Actually I read the first 2-3 pages of the article. It doesnt even mention PowerPC until the section on architecture-specific optimizations, and everything above that is 'duh, i already know -O2 does' material

Re:What?

[den_erpel]

Perhaps you should have a look at Wikipedia [wikipedia.org]. It is the base for a lot of processor architectures, including PowerPC. A lot of embedded architectures use a PowerPC instead of an Intel or other uC.

Considering the spread, I for one am interested very interested in the article and esp. in order to see what kind of improvements gcc can still obtain. This gives me a very strong incentive to keep a close eye on the development and re-create my crosscompilation environment with major and mid gcc releases.

Re:What?

[__aaclcg7560]

It's a relevant question. After scanning over the article, I would've never figured out that POWER stands for PowerPC. Duh! The problem is the summary and the article is not clear on this point. Not everyone is well versed on the CPU designs outside of Intel and AMD.

Re:What?

[0racle]

Could that be because Power doesn't stand for PowerPC. PPC is just one chip type in the Power family. Its an article summary, not glossary. If you don't know what something is, look it up yourself.

Power PC rocks !!

[Gopal.V]

PowerPC CPU is a cool design - not only does it deliver great performance at lower clock speeds, but the entire design is great for compiler devs .

For one, they have true 3 register operations. Which means that every binary operation has a src1, src2, and dst. Also all opcodes are 32 bit - no exceptions (jmp offsets are easy to check for).

Because of 32 registers (not a measly 8), most of the code can run very fast off them , especially those tight loops. Also the cache touch instructions which do not segfault for invalid addresses helps you fetch arrays before their indexes are validated.

All in all, I prefer PPC to x86 on any day. Now if only they'd have a common FPU opcode set.

Re:Power PC rocks !!

[keesh]

Uh, you just described SPARCv9, not Power. Power opcodes come in multiple sizes.

Not quite the operator I'd use...

[Millennium]

It's more accurate to say that PowerPC POWER, rather than that PowerPC != POWER..

There are several lines of chips based off of the POWER architecture. PowerPC is one of them, and as others have mentioned it has fixed-size 32-bit instructions. It's a subset of the POWER architecture which has this particular property, but that property might not apply to POWER itself.

Nothing to see here...

[Anonymous Coward]

Look, I'm all for optimizations and compiler technology, but the example is *lame*. First it's copying gigs of memory from one array to the other in a _non-sequential_ (!) manner. I think it is safe to say that by reordering the loops you would get all the benefits of the IBM compiler. Why not use the memcpy() function then??

I think the lesson here is not how a compiler can save you time but how you can save time by not reading the article.