AMD Unveils SSE5 Instruction Set 85
mestlick writes "Today AMD unveiled its 128-Bit SSE5 Instruction Set. The big news is that it includes 3 operand instructions such as floating point and integer fused multiply add and permute.
AMD posted a press release and a PDF describing the new instructions."
Who cares... (Score:1, Insightful)
Well, I'm excited. I think. (Score:5, Insightful)
Foundations for the GPU+CPU assimulation... (Score:5, Insightful)
It'll take a couple years for "SSE5" to show up in AMD chips... which happens to coincide nicely with their Fusion (combined CPU+GPU) product line plans.
Will Intel pick up on these instructions? Maybe not. Does that mean they die? No, the performance benefits for those areas where this will make the most difference will make it worthwhile. At the very least, AMD can sponsor patches to the most popular bits of OSS to earn a few PR points (and benchmark points).
Re:Well, I'm excited. I think. (Score:2, Insightful)
Re:Cryptographer's Take? (Score:3, Insightful)
What about 256 bit? (Score:3, Insightful)
Sure multimedia & games use lower precision FP computations so 16b or 32b FP number is enough, but it's strange that AMD doesn't try to improve the usage for the scientific computation niche.
Maybe it's because the change would be expensive as to be efficient, the width of the memory bus should be expanded to 256b from 128b now.