AMD Unveils SSE5 Instruction Set 85
mestlick writes "Today AMD unveiled its 128-Bit SSE5 Instruction Set. The big news is that it includes 3 operand instructions such as floating point and integer fused multiply add and permute.
AMD posted a press release and a PDF describing the new instructions."
Re:APL (Score:2, Interesting)
Re:Well, I'm excited. I think. (Score:4, Interesting)
I don't write those fancy codecs, but I can immediately see where some of these instructions could come in handy - for instance, PCMOV and PTEST (packed cmov/test).
The new instructions take up an extra opcode byte, but seeing how they will lower the amount of instructions you would otherwise do, I don't see that as a problem. The super instructions (like FMADDPS - Multiply and Add Packed Single-Precision Floating-Point) do more than just help the instruction decoder too - they mention "infinitely precise" intermediate voodoo for several of them which makes it seem like doing a FMADDPS instead of a MULPS,ADDPS will result in a more accurate result.
There are new 16-bit floating point instructions too, which I can see as a boon for graphics wanting the ease of floating point and a little higher rounding precision than bytes with values between 0 and 255 would give, without the large memory requirements of 32-bit floating point.
Re:Foundations for the GPU+CPU assimulation... (Score:3, Interesting)
Gamers can still buy addon graphics cards, of course.
Re:Cryptographer's Take? (Score:3, Interesting)
One useful addition (copied from Altivec) is the vector permute instruction. What is clever about it in terms of cryptography is that you can translate a vector using a 256 byte translation table _without doing any memory access_ by using the vector permute instruction in a clever way. Now the execution time is completely data-independent, so one important attack vector is closed.
AMD just forked x86 (Score:2, Interesting)
Here's some more information: http://www.anandtech.com/cpuchipsets/showdoc.aspx
AES - how is speedup achieved? (Score:3, Interesting)
Anyone got any guesses? Someone who understands Matsui's recent work on bitslice AES implementations better than I do? Will this implementation be resistant to lookup-based side channel attacks?